1. Field of the Invention
The invention relates generally to memory clock generation and, more particularly, to memory clock generation with configurable phase advance and delay capability.
2. Description of the Related Art
Memory clock generation is a critical component of a memory subsystem implementation and affects the overall memory interface timing budget. The memory subsystem clock generation and timing is particularly critical for existing memory technologies such as synchronous dynamic random access memory (SDRAM) and static random access memory (SRAM), and more so for emerging memory technologies, such as double data rate (DDR) SDRAM and quad data rate (QDR) SRAM, that employ source synchronous clocking schemes.
Conventionally, memory clock adjustment support has been designed into the system board using fixed wire delay schemes to add or remove delay on the order of hundreds of pico seconds. However, this method is not flexible enough to allow the user to compensate for board deficiencies and make a broader range of adjustments, given the strict timing requirements of emerging memory technologies such as DDR SDRAM and QDR SRAM.
Therefore, there is a need for a high degree of control and flexibility in the memory clock generation such that the memory-clock relationship, with respect to the memory command and data, can be adjusted independently, thereby creating the ability to effectively adjust the memory interface timings such as setup time, hold time and memory read data access time.
The present invention provides a memory clock generation logic circuit comprising a configuration register including desired phase shift and time delay values, and circuitry for applying those values to a synchronization signal. The synchronization signal is shifted 0-, 90-, 180-, or 270-degrees according to the desired phase shift value. Additionally, the synchronization signal is delayed according to the desired time delay value. The combination of the phase shifting and the time delaying provides a method and an apparatus that allow for the fine tuning of the synchronization signal.